1. Field of the Invention
The present invention relates generally to semiconductor devices. More particularly, the present invention relates to forming an isolation structure in a substrate.
2. Background of the Invention
With increasing Large Scale Integration and smaller semiconductor device sizes, there is a greater risk of unwanted interferences between semiconductor components. Components must be properly isolated to prevent current leaks or voltage breakdowns between junctions. This is especially true for high-voltage components. Present methods for generating isolation regions are compromised by STI-CMP (shallow trench isolation chemical mechanical polishing) constraints. Conventional methods don't tend to generate relatively impermeable and stable isolation regions, especially for high-voltage applications.
In a substrate of single crystalline silicon, semiconductor devices are formed in what are known as active regions. These active regions need to be electrically isolated from each other. This can be done by removing portions of the substrate, thereby creating a trench or recessed layer between the semiconductor devices. A dielectric layer is introduced into the trench or recess to create the isolation region. Such a technique is commonly referred to as shallow trench isolation (STI).
On a more specific level, this known technique involves applying a blocking layer over the silicon substrate, selectively removing portions of the blocking layer and the substrate where an isolation region is needed, oxidizing, and then depositing the dielectric layer over the blocking layer and in the trench or recess. Then, a chemical-mechanical polishing (CMP) step is carried out on the dielectric layer in order to remove portions of the dielectric layer disposed above the blocking layer, while leaving a planarized portion of the dielectric layer in the trench or recess. A small portion of the blocking layer may be incidentally removed with the upper portion of the dielectric layer.
There may be variations in dependence on the size of respective active regions which are near each other, because the chemical-mechanical polishing process tends to remove material more rapidly over smaller active regions than over larger active regions. This can be cured by providing dummy moats or dummy active regions, which are similar to true active regions except that no components are ultimately fabricated in these dummy regions. The purpose of these dummy active regions is to increase the cumulative area of active regions present in certain portions of the wafer.
However, there are several problems with dummy moat generation as practiced today. Dummy moats are generated using a set of rules. These rules determine the moat area and placement, and these moats are patterned before and during the STI-CMP process. When the diffused layers are subsequently silicided, the dummy moat is also silicided. Thus, a dummy diffused layer will have a silicide layer on top of the remaining non-alloyed part. Where in CMOS applications, the diffusions are small so the dummy moat area need not be large, this is not a problem. However, in higher-voltage applications, diffusions are large so inevitably, a larger junction area is covered. Since the dummy moat is typically silicided, when a dummy moat resides across a junction region, the threshold breakdown voltage across the junction is lowered, leading to shorts across the junction.
Also, suicide dummy moats located near or across junctions could short the junctions. Therefore, dummy moats have to be kept out as far as 12 μm for high voltage devices, leading to further STI-CMP process issues.
Conventional efforts to curb this problem have focused on excluding any dummy generation around the junction areas. These exclusion zones result in a reduction in the overall moat density. This causes problems with the STI-CMP process as described above because a larger moat area gives more uniform CMP results. Also, exclusion zones for high-voltage devices must be larger, which raises issues with dummy moat density rules. What is needed is an improved method to generate dummy moats without reducing the moat size/density while maintaining a high breakdown voltage.